As the integration density of integrated circuits continues to increase, the size of the individual active devices such as field effect transistors, also generally continue to decrease. With the decreased feature size, it may become increasingly difficult to electrically contact the active device regions.
For example, a dynamic random access memory (DRAM) integrated circuit device generally includes contact windows which connect a cell transistor source region to a respective storage electrode of a cell capacitor. Contact windows are also included to connect the cell transistor drain regions to respective bit lines. In order to increase the device integration, the contact windows preferably should be small, preferably smaller than the resolution limits of the exposure tools which are used to form the device.
Self-aligned integrated circuit fabrication methods have been developed to form small contact windows. One example of a self-aligned method forms a self-aligned contact window which exposes the source and drain regions and forms a landing pad on the exposed source and drain regions to permit contact to a storage electrode or bit line as required. FIGS. 1A-1I are cross-sectional views which illustrate a method of fabricating field effect transistors in a conventional semiconductor memory device using self-aligned contact window formation and landing pad formation.
Referring now to FIG. 1A, an integrated circuit memory device includes a cell array portion which includes a plurality of memory cells therein, and a peripheral circuit portion which includes a plurality of peripheral circuit transistors. As shown in FIG. 1A, a plurality of spaced apart gates are formed on an integrated circuit substrate. In particular, a plurality of gate electrodes 12 are formed on an oxide layer 9 on a semiconductor substrate 10. The gate electrodes 12 are covered by a capping layer 11. A plurality of P-type source/drain regions 14 and N-type source/drain regions 16 having relatively low doping concentrations, are formed by implanting P- and N-type dopants into the PMOS and NMOS transistor regions respectively, using the gates as a mask. A first insulating layer 18 is then formed by coating the substrate with an insulating material such as silicon dioxide. A second insulating layer 20 is then formed by coating the first insulating layer 18 with a second insulating material such as silicon nitride.
Referring now to FIG. 1B, the substrate is then coated with a photoresist which is then patterned to form a first photoresist pattern 22 which exposes the peripheral circuit portion of the device. First spacers 24 are then formed on the sidewalls of the gate electrodes 12 of the peripheral circuit portion by anisotropically etching the exposed first insulating layer 18 using the first photoresist pattern 22 as an etch mask.
Then, in FIG. 1C, the first photoresist pattern 22 is removed. The surface of the substrate is coated with photoresist and patterned to form a second photoresist pattern 26 which exposes only the NMOS transistors of the peripheral circuit portion. The source/drain regions 17 of the NMOS transistors in the peripheral circuit portion are then formed by implanting high concentrations of N-type dopants.
Referring now to FIG. 1D, the second photoresist pattern 26 is removed and the substrate is again coated with photoresist and patterned to form a third photoresist pattern 28 which exposes only the PMOS transistors of the peripheral circuit portion. Source/drain regions 15 of the PMOS transistors of the peripheral circuit portion are then formed by doping P-type dopant at high concentration.
Referring now to FIG. 1E, the third photoresist pattern 28 is removed and an insulating layer 30 is formed on the substrate. A photoresist is formed on a substrate and patterned to form a fourth photoresist pattern 32 which exposes the cell array portion of the integrated circuit. Then, as shown in FIG. 1F, the fourth photoresist pattern 32 is used as an etch mask and the insulating layer 30 in the cell array portion is removed using dry or wet etching. The insulating layer 30 which protects the peripheral circuit portion, remains in the peripheral circuit portion.
Referring now to FIG. 1G, the second insulating layer 20 is removed by dry or wet etching. Second sidewall spacers 25 are then formed on the sidewalls of the gate electrodes 12 of the cell array portion by anisotropically etching the first insulating layer 18. The fourth photoresist pattern 32 is then removed.
Referring now to FIG. 1H, source/drain regions 19 having relatively high doping concentrations, are then formed in the cell array portion transistors by forming a polycrystalline silicon (polysilicon) layer 34 on the surface of the substrate and doping the polysilicon layer with N-type impurities. A fifth photoresist pattern 36 is then formed on the polysilicon layer 34. The fifth photoresist pattern 36 is then patterned to permit forming of landing pads.
Finally, in FIG. 1I, a landing pad 35 which contacts the source/drain 19 of the transistors of the cell array portion is formed by anisotropically etching the polysilicon layer 34, using the fifth photoresist pattern as an etch mask.
Unfortunately, in the above-described method, the source/drain region 19 of the cell array transistors and the landing pads 35 therefor are formed after the source/drain regions 15 of the peripheral circuit portion transistors. This may complicate the fabrication process because of the insulating layer 30 which protects the peripheral circuit portion during landing pad fabrication. This process complexity may increase the manufacturing cost and decrease the device yields.